SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate

This paper presents a transistor sizing algorithm and utility for soft-error (SER) protection circuits. The algorithm applies a gradient-descent convergence scheme for rapidly calculating an optimized sizing configuration per specific protection circuit instance. The utility efficiently interacts with commercial SPICE circuit-level tools for highest accuracy. The analysis and optimization flow is distributed over parallel compute resources to provide a scalable and feasible solution for large designs. The solution is demonstrated on two configurations of the Muller C-element circuit, a widely used component for SER protection across designs. By sizing the test circuits with the proposed utility, a SER protection improvement of as much as two orders-of-magnitude is achieved over a baseline design within minutes of compute runtime.