VLSI Implementation of Accuracy Configurable Radix-4 Adder for Digital Image Processing Applications

The performance of real-world integrated circuits. This work is focused on implementation of novel architecture of Accuracy Configurable Radix-4 Adder (ACRA) utilizing full carry generation (FCG), full sum generation (FSG), half carry generation (HCG), and half sum generation (HSG) blocks, which is named as Hybrid ACRA. Further, the N-bit Hybrid ACRA is implemented using reconfigurable properties with square root additions through modified sum carry selection-based Radix-4 properties. Further, the Carry and Sum output generation consumes less propagation time by utilizing multiplexer switching logic, which selects the full sum bits and carry bits in high-speed manner. The simulation outcomes show that the proposed Hybrid ACRA resulted in improved area, delay and power consumptions as compared to the basics adders and state-of-art approaches.