On the JEDEC Board Level Drop Test Simulation of Array of BGA Packages

Drop test durability has been a major concern for devices widely used in mobile applications. JEDEC standard is introduced to characterize IC package drop performance such that a consumer product manufacturer could have a readily available benchmark to assess reliability of components from different suppliers under the same test conditions. At first explicit solvers were extensively used to tackle the free fall problem due to its transient and dynamic nature. They were soon simplified to Input-G method to avoid complexity in modeling contact event. Still their inherent poor numerical stability during simulation has limited its application to drop events with small to medium size unless the analysis utilizes very fine time incremental steps, which, in turn, is time consuming. In addition, many component suppliers usually do not have such software. Therefore, implicit solver has recently been employed to simulate board level drop test. Its limitation lies with its connate incompatibility with the direct application of the base acceleration profile but can be overcome by additional treatment of the boundary conditions. This paper investigates the simulation methodologies of JEDEC board level drop test using implicit solver. It demonstrates that both Direct Acceleration Input (DAI) method and Large Mass Method (LMM) could be used to model the current industrial specified drop test, which is a moderate transient process, but the latter is a better option as it captures the real response of the package assembly under test. Actual drop tests were carried out and compared with simulation predictions, they are found in good agreement. Further examination of the current common industrial practice raises concerns about the accuracy of its data collection and interpretation of JEDEC board level drop test results. Possible solutions are offered for improvement of board design and data analysis.