Influence of Ball Grid Array Design Parameters on Solder Joint Reliability

Ball grid array (BGA) package is widely used in electronic packaging. This type of package can accommodate high I/O in the small form factor package size compared to the quad-flat package (QFP) and quad-flat no-lead (QFN). Due to its function to electrically connect the package substrate to the printed circuit board (PCB), it is important to ensure the 2
^nd
level interconnect is reliable against cyclic thermo-mechanical load. Ever-increasing functional density in microelectronic components requires a continuous redesign of packaging technology. Characteristic attributes are form factor, pin count, pitch, power density, diverse application and harsh environment. Packaging engineers have to ensure new product designs will act according to specifications and will survive in the field for the targeted market. The interconnection of the semiconductor package and PCB is one of the most critical elements in the electronic control unit. A thermal mismatch between component and PCB, together with varying temperatures causes cyclic deformation and fatigue of solder interconnect. The semiconductor manufacturers apply an accelerated temperature cycling test to assess the risk for early failure in the field. To reduce the development cycle, NXP is applying virtual prototyping and testing by simulation. This allows to run extensive design studies in a relatively short time with only a few prototype builds for empirical validation. NXP has established robust simulation technics for the assessment of fatigue in solder alloys. In this paper, we want to share a design study for BGA. We will derive the significance of various design parameters concerning the solder joint reliability in a board assembly. For instance, we will assess the influence of PCB pad diameter, solder stand-off height, solder alloy materials, die sizes and package core thickness. The simulations described in this paper are done during the early design stage to ensure all NXP products are robust and reliable. To evaluate the relative failure risk between design cases, a volume average approach on the accumulated creep energy density is used. We will discuss the significance of mentioned design parameters with respect to the board-level reliability test conditions. We will provide, a few guidelines from a mechanical standpoint to mitigate solder joint bulk fatigue under board level temperature cycling (BLTC) test conditions.