An improved LDMOS-SCR design for high-voltage ESD

In this paper, a
$0.18-\mu m$
BCD technique was used to design an I-LDMOS-SCR with a high holding voltage. According to the results of the Transmission Line Pulse Test (TLP), the I-LDMOS-SCR has a holding voltage of up to 20.8V, which is suitable for ESD protection against high voltage applications.