Clock Shift and Sampling Delay Effects on Stability in Digitally Controlled Cascaded DC-DC Converters

Interactive digital control using PMBus protocol can significantly improve performance, efficiency and reliability in high frequency low voltage DC (LVDC) microgrid applications using online optimization through shared clock and data. Modeling and analysis of digitally controlled standalone DC-DC converters, considering finite sampling delays, have been well reported in the past; however, modeling and analysis of fast scale stability and performance limits, under finite sampling delay and clock shift, have not been investigated so far in digitally controlled LVDC microgrids. This paper considers an intermediate bus architecture (IBA), consisting of an intermediate bus converter (IBC) followed by a point-of-load (PoL) converter, under clock-synchronized digital current mode control (DCMC). Considering the IBA dynamics, a discrete-time (DT) framework is proposed, and DT small-signal models are derived for stability and performance analysis. It is shown that the clock shift between individual converters and the sampling delays of their corresponding digital controllers have significant impacts on the fast-scale stability of the overall IBA system, which may lead to severe fast-scale instability with complex nonlinear phenomena and resulting in much higher (inductor) current ripple and RMS quantities. Simulation case studies are presented, and the stability boundaries are found to be consistent with the analytical predictions. The proposed framework will be helpful to design stable digital control in DC microgrids.