Productivity optimization techniques for the proactive semiconductor manufacturer

Summary form only given. The experienced semiconductor manufacturer is often confronted by apparently similar products that yield drastically different productivities. The same processes are used to fabricate these chips, yet the manufacturer's costs are clearly different. The customers expect similar pricing and a deviation must be accompanied by a credible explanation. Design for manufacturability (DFM) has become a popular industry term, yet many chip designers are uncertain where to start and what to implement. The semiconductor manufacturer possesses knowledge or suspicions of potential barriers and improvement opportunities. This information must be proactively fed forward to the design shops, which must also budget resources and time to address these items. This presentation describes how this process works, illustrated with examples from IBM Microelectronics' Vermont facility. Before focusing on productivity optimization, a recommended set of metrics is identified, and the concept of physical design characterization is overviewed. Past and existing designs provide excellent historical insight into a large number of issues that are often independent of technology node. While robust technology development objectives strive to minimize the potential manufacturing stumbling blocks, competitive pressures will balance these with other constraints. Ultimately, it is decisions made by a designer that will determine the level of productivity achievable. Much of this presentation is devoted to describing a number of these decisions. In addition, the manufacturer may deploy complex algorithms to adjust the design to process constraints. Another, but more costly solution is for the manufacturer to tailor the process to a specific product, compensating for identified product-technology gaps. Lastly, this presentation ties these concepts together into a recommended business process.