A Compact D-Band CMOS Frequency Sixtupler Using a Mode Analysis of the Harmonics

A miniaturized D-band frequency sixtupler using a mode analysis of the harmonics is proposed to improve the output power of the CMOS process using a low driving signal. The operation mode of the harmonics in a differential frequency multiplier is analyzed to independently control the behavior at odd- and even-order harmonics. The proposed CMOS sixtupler consists of a tripler, a buffer amplifier, a push–push doubler, and impedance matching networks. The interstage network between the tripler and the buffer amplifier performs impedance matching of the desired frequency and filtering of unwanted signals. The network between the buffer and the doubler simultaneously performs impedance matching while acting as the harmonic reflector. The output power of the doubler located at the final stage of the sixtupler is improved by LC source degeneration, providing LC resonance, and a high impedance condition at the second-harmonic frequency. The proposed sixtupler was implemented in an area of 0.4 mm2 using the 65-nm CMOS technology. The measurement results indicate a saturated power of −1.2 dBm with a harmonic rejection ratio (HRR) of 25 dBc for an input driving power of 15.5 dBm at 148.2 GHz. The maximum conversion gain (CG) is −0.7 dB at a low driving power of −6.5 dBm at 150.6 GHz.