The Effects of Voids on Solder Joint Reliability in First Level Interconnect

First level interconnect (FLI), e.g. flip-chip attach on substrate or wafer, using solder as the interconnect material, is employed extensively in the advance packaging assembly. During the flip-chip die attach process, voids are often formed in the solder joints. In the past this was not seen as a major issue due to void % being typically lower than 10%, but as miniaturization continues, the solder joint of FLI is becoming smaller (<100um bump or Cu pillar size) with tighter pitch and higher density. This has resulted in an increasing concern on how the micro voids in the solder joint will affect the package’s long-term reliability, despite the void % being low. In addition, a literature search on the web shows that there is limited research done on this subject. During the first phase of this project, process recipes were defined to consistently build packages both with and without solder voids. The appropriate X-ray inspection tools and CT were used to determine the size and location of the macro and micro voids in the FLI solder joints. It was found that packages built using solder paste typically had more voids in the solder joints when compared to packages built using flux and solder sphere process. Subsequently, test packages built in the first phase, both with and without micro voids, were subjected to different reliability tests, i.e. thermal cycling tests, electromigration tests and thermal shock tests. Observations from the test results showed that test packages with solder voids generally performed worse in solder joint reliability when compared to the test packages without solder voids. It was also observed that voids can create current crowding in the area surrounding them, which accelerates electromigration degradation, with larger voids having more significant impact from the simulation model. Consistent with other studies, greater electromigration degradation occurred in joints where the orientation of Sn grains are aligned along the c-axis and parallel to the current flow direction. This paper will describe the details of the different test conditions, and discuss observations from the failure analysis done with cross-sections and EBSD analysis.