Reliability of ultra thinning of flip chips for through-silicon analyses

In this paper, we address the issues of global ultra-thinning (/spl les/10 /spl mu/m) of flip chips and develop a reliable and inexpensive process based on a conventional lapping tool and a compact thickness monitoring system. The mechanical and electrical yields as a result of ultra-thinning are reported. The commonly seen die warpage in flip-chip packaging is discussed and addressed in the thinning process since the warpage level can be much more than the final target thickness. Finally we present preliminary results using a CNC milling approach with hope to open the door to generalizing silicon ultra-thinning on all types of IC packages.