A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS

This article presents a four-level pulse-amplitude modulation (PAM-4) transceiver targeting very-short-reach and medium-reach (MR) electrical links. The receiver (RX) employs a sample-based four-tap feed-forward equalizer (FFE) for pre- and post-cursor inter-symbol interference (ISI) compensation. The two-stage 16-way interleaving provides sufficient operation time for FFE summation, which relaxes the bandwidth (BW) requirement and improves power efficiency. The non-uniform segmented three-tap FFE reduces the parasitic capacitance in the transmitter (TX). The one-unit interval (UI)-pulse generator in the 4:1 multiplexer uses a pre-charge phase to achieve a fast edge with single-stage logic. Fabricated in 28-nm CMOS technology, the transceiver achieves a bit error rate (BER) of < 1
$e-11$
at 112-Gb/s transmission with a channel loss of 20.8 dB and an energy efficiency of 2.29 pJ/b.