Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications

A blocker-tolerant harmonic selection receiver front-end with RF bandwidth of 6.5 GHz to support the fifth-generation (5G) sub-6 GHz band is presented. The proposed N-path switching filter-based receiver employs harmonic recombination blocks at the baseband (BB) to select the desired local oscillator (LO) harmonics and suppress blockers. It is demonstrated how the configuration of two feed-forward N-path switching filters and BB harmonic recombination stage can be reconfigured to select the first harmonic of the switching frequency at the low-frequency band (0.5–1.9 GHz) and the third LO harmonic at the high-frequency band (1.95–6 GHz). Thus, the proposed architecture has the capability of supporting an RF input frequency of up to 6 GHz while the switching frequency operates up to 2 GHz. Higher harmonic selection in addition to the fundamental helps to reduce the power consumption and required input frequency of the multiphase LO clock generator. An RF receiver prototype is fabricated in a TSMC 130-nm CMOS technology. It achieves a 5 dB noise figure (NF), −16.6 dBm in-band input-referred third-order intercept point (IIP3), and 9 dBm out-of-band (OOB) IIP3, respectively, at the low-frequency band (0.5–1.9 GHz). The 2nd–5th harmonic rejection ratios (HRRs) are higher than 44 dB without any calibration. The receiver can tolerate a 0 dBm blocker at a 180 MHz offset from a 1 GHz switching frequency with an NF of 9.4 dB. Over the high-frequency band (1.95–6 GHz), the receiver’s NF is less than 7.1 dB. Moreover, in-band IIP3, OOB IIP3, and first HRR are higher than −21 dBm, 7 dBm, and 39 dB, respectively. The receiver achieves an S11 better than −10 dB over 0.5–6 GHz, and has a total power consumption of 17–22.5 mW from a 1.2 V supply.