Sensitivity Investigation of Planer Ground Plane Junctionless Transistor (GP-JLT) for UVA Photodetector

In the present work, the suitability of bulk junctionless transistors (JLTs) having a ground plane (GP) layer within buried oxide (BOX) (i.e., HfO2 as oxide material) has been demonstrated for detecting long-wavelength ultraviolet (UVA) light (i.e., in the range of 315–400 nm). Comparisons have been performed with the conventional bulk silicon on insulator (SOI) JLT to explore the suitability of the incorporated GP in the high-
${k}$
BOX region for the detection of UVA light. The incorporated GP in the SOI JLT (having high-
${k}$
BOX) spreads the electric field (EF) toward the drain side, which further signifies diminished leakage current (at zero gate bias) and hence higher sensitivity against the UVA light. Improvement in the device sensitivity against the UVA light has also been observed by tuning the GP depth (
${d}_{\text {GP}}{)}$
(i.e., lower
${d}_{\text {GP}}$
results in improved sensitivity (
$3\times 10^{{3}}$
to
$1\times 10^{{5}}{)}$
and higher
${I}_{\text {on}}/{I}_{\text {off}}{)}$
. The doping of the GP layer at
${d}_{\text {GP}} =10$
nm further helps in improving the device sensitivity, especially from
$3.4\times 10^{{3}}$
to 1.73
$\times 10^{{5}}$
which is almost similar to the sensitivity achieved from the device at
${d}_{\text {GP}} =$
4 nm (i.e.,
$2.2\times 10^{{5}}{)}$
. Using S/D having a workfunction of 3.9 eV, further improvement in sensitivity has been achieved, which is significantly high at
${d}_{\text {GP}} =10$
nm (almost double) when compared to
${d}_{\text {GP}} =$
4 nm (18% improvement in the
${I}_{\text {light}}/{I}_{\text {dark}}$
ratio). The high-
${k}$
gate oxide also enhances the device sensitivity at the cost of increased decay time (i.e., when the device is completely turned off). Results also demonstrated that the impact of parameter variation is lower at
${d}_{\text {GP}} =$
4 nm compared to
${d}_{\text {GP}} =10$
nm.