A MEOL logic layout optimization recommendation under 3 nm CFET architecture and beyond

In order to continue the area shrink of the integrated circuit area, besides patterning technology improvement, an introduction of Complementary Field Effect Transistor (CFET) has been proposed for 3 nm logic node ^[1]-[2]. We have designed an SRAM under CFET architecture, where a N-type Metal Oxide Semiconductor (NMOS) is stacked on top of a PMOS. The method of local interconnect of two groups of MOSFETs (PMOS and NMOS) is critical to the area of this SRAM unit cell. We have used our self-developed Extreme Ultra-Violet (EUV) process simulation code with photon absorption stochastics ^[3]-[5] to study a 3 nm CFET SRAM processes. In addition, according to our previous study on the industry standard of the photolithographic process, we have incorporated the photon absorption stochastics and determined the EUV process window industry standard for the future technology nodes ^[6]. From the perspective of the industry standard, we have found that once the 45° local interconnect is adopted, this SRAM unit cell can reach a minimum area of ~ 0.0115μm². However, if we keep the original square local interconnect design, the cell height needs to be increased from 5 fin pitches (FPs) to at least 6 FPs with the SRAM unit cell area increasing by at least 20%.In this paper, we will study the process window of the original square local interconnect designs with stitching in both low and high NA EUV lithography and the corresponding minimum SRAM area.