A Low-Power Low-Pass Filter for Noise Suppression in Chopped Bioamplifiers

1/f noise and low-frequency offset of CMOS amplifiers greatly influence the performance of bio-signal acquisition. Besides, intermodulation distortion can occur when the input signal interacts with the chopper clock. A conventional chopper amplifier consumes large power and silicon area because it requires specific techniques or a low-pass filter (LPF) with a large time constant to eliminate modulation noise. In this paper, an improved chopper amplifier using recycling folded cascode architecture with a power- and area-efficient LPF is designed and simulated in TSMC 40-nm process. The overall topology consumes 5.57 μW power with a bandwidth of 2.2 kHz, while the proposed LPF only consumes 0.97 μW with a chip area around 0.0086 mm². The input-referred noise is 1 μVrms integrated from 0.1 Hz to 200 Hz.