A Column-parallel SAR/SS ADC with Multi-column Shared Capacitor DAC for CMOS Image Sensor

This paper presents a 12-bit column-parallel two-step SAR/SS ADC with multi-column shared capacitor DAC for CMOS image sensor. A 7-bit capacitor DAC is used to coarsely quantize the inputs of 4 columns in sequence, and a 5-bit ramp generator is used to finely quantize the inputs of all columns at the same time. Hybrid two-step ADC consisting of SAR and SS significantly improves A/D conversion speed, and the multi-column shared capacitor DAC obviously reduces the limitation on circuit area due to the column width, which is determined by the pixel size of CMOS image sensor. The circuit is implemented in UMC 110nm CMOS process with a 3.3V/1.2V power supply. The simulation results show that, SFDR, THD, SNDR and ENOB are 82dB, -86dB, 69dB and 11.17-bit with the input frequency of 35.487kHz at 357KSps sampling rate, respectively.