Hollow Airgap Technology for CMOS Maximum Interconnect Capacitance Reduction

A flexible air gap technology to form ultralow-k
eff
dielectric CMOS interconnect with a large void fraction is described in this work. The air gap can be supported by the interconnect metal and dielectric pillars to achieve a global void fraction >75%, achieving a global k
eff
below 2.1 with sufficient mechanical strength. The technology can be extended to form hollow structures using multi-level air gaps. Careful placement of dielectric pillars around the signal lines of interest, along with air gaps between adjacent lines, results in even a lower k
eff
, limited by the higher-k etch-stop layer. This is equivalent to a low-k dielectric with 85% porosity but with Young’s modulus of >20 GPa, beyond theoretically achievable by the existing low-k approach.