Ultralow On-Resistance Integrated Vertical DMOS Embedded into 0.18μm BCD Process

This paper presents the vertical DMOS structure integrated into CMOS flow, which is demonstrated from the TCAD and silicon proven. With the source contact at the bottom of the trench, the device prototype can achieve the vertical trench DMOS experimental physical structure and best-in-class performance of the specific on-resistance (Ron,sp) about 12 mΩ•mm
²
with the breakdown voltage (BV) about 50V. This performance is better around 20% than the lateral DMOS for the operating voltage of 30V level. Furthermore, the body diode current density performance is effectively enhanced due to the schottky contact and the gate charge (Qg) is also lower than that of lateral DMOS for higher efficiency of the switching converter.