Investigation of Parasitic Capacitance Effects in V-GAA Transistor via 3D PEX Methodology

In this work, the parasitic capacitance of the V-GAA transistor structure was successfully extracted, which suffer from the different pillar size in SADP process. Such as pillar height and width. Based on the range of λ from 0.85 to 1.15, the variation of gate around capacitance with the pillar height and width is less than 1.6% and more than 15%, respectively. In addition, the pillar width is the main factor affecting the coupling capacitance of V-GAA array structure. This provides fundamental research for further device study of V-GAA in the far technology node.