A 6b 800MS/s SAR ADC With Speed-Enhanced SAR Logic and Grouped DAC Capacitors

This paper presents a 6-bit 800MS/s successive approximation register (SAR) analog-to digital converter (ADC) in 28nm CMOS with grouped digital-to-analog converter (DAC) capacitor array. High-speed operation is achieved by improving the control logic and using custom-designed unit capacitor of comb structure. At 800MS/s sampling rate with Nyquist input, the post simulated SNDR and SFDR are 37.68dB and 50.1dB respectively, and the ADC core consumes 1.82mW from 1V supply, achieving 36.5fJ/conversion-step.