A 8.5 fJ/Addition Dynamic Analog 8-3 Compressor for Energy Efficient Computing-in-Memory Macros

This paper proposes a dynamic latch-based mixed-signal 8-3 compressor used for multiplication-accumulation (MAC) operation for computing-in-memory (CIM). This compressor is based on StrongARM dynamic latch and adopts digital input and charge-steering design paradigm, which makes it has a low computation error rate and low power consumption. The compressor converts digital input to digital output directly, avoiding power-hungry ADCs, it has better error rate and energy efficiency than the charge domain accumulation circuit commonly used in the computing-in-memory circuit. The circuit is implemented in 65nm LP process, achieving 8.5fJ/addition under 1.08V supply and 200MHz operation frequency.