A 12-bit 20MS/s Asynchronous SAR ADC

A 12bit 20MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Segmented DAC technology and merged capacitor switching (MCS) are applied to reduce chip area and power dissipation. A floating inverter amplifier (FIA) assisted comparator is used to reduce noise and power consumption. The ADC is designed and simulated in a 180nm CMOS process. The simulation results show that the ADC consumes 1.3mW, achieving 70.48dB SNDR at 20MS/s, resulting in an SNDR-based Schreier figure of merit (FoM) of 169.3dB.