Benchmarking Frequency-Dependent Parasitics of Fine-Pitch Off-Chip I/Os for 2.5D and 3D Heterogeneous Integration

Extremely low-latency and wide-bandwidth signal communication between processors and memories is driven by applications such as high-performance computing (HPC). Heterogeneous integration with short-reach parallel signal interfaces can meet these demands with low cost, high yield, and low power. To increase the bandwidth of the signal interfaces, high I/O density is needed and off-chip I/O with finer pitch becomes critical. However, a finer pitch leads to higher I/O resistance that degrades the signal integrity. In this article, for the first time, an extraction of frequency-dependent parasitics (100-GHz bandwidth) is utilized along with numerical calculations to perform a comprehensive study of underfill (UF) effect, substrate effect, the impact of pitch scaling, and the impact of ground-signal (G-S) configuration for future fine-pitch (down to $2 \mu \text{m}$ ) off-chip I/Os, including solder bump, microbump, and hybrid-bond. Hybrid-bond possesses extremely lower parasitics (14.4–22.3 $\text{m}\Omega $ , 1.1 pH, 0.17 fF at 10- $\mu \text{m}$ pitch) than microbump with the same pitch, which shows its potential as mainstream off-chip I/O for < 10- $\mu \text{m}$ pitch. However, the resistances of hybrid-bond and microbump increase rapidly with pitch reduction. For the high resistance, one promising solution using the design of G-S configuration is studied for hybrid bonding and microbump technology in this article.