A New Layout Method for Junction Field Effect Transistors (JFETs) on 4H-SiC that Provides a Significant Reduction in On-Resistance

In this work, we demonstrate a new layout technique for 1.2kV-rated lateral-vertical 4H-SiC JFETs that provides a 21% reduction of the specific on-resistance (R
on,sp
) when compared to JFETs using the conventional stripe layout. Both the proposed and conventional layouts were fabricated on the same substrate and achieved a R
on,sp
of 3.13 mΩ-cm
²
and 3.97 mΩ-cm
²
at a VGS of 0 V and 2.46 mΩ-cm
²
and 3.12 mΩ-cm
²
at a VGS of 2 V during on wafer measurement, respectively. Additionally, the proposed layout approach showed no adverse influence on the blocking characteristics of the device. The demonstration of this proposed layout approach shows the high-performance potential of 4H-SiC JFETs.