A Fully Integrated 1 MHz – 2.5 GHz Radiation-Hardened All-Digital Frequency Synthesizer

A fully integrated radiation-hardened all-digital frequency synthesizer, fabricated in a commercial CMOS technology, is presented. Single event monitoring of the Phase-Locked Loop (PLL) is proposed by comparing the Time-to-Digital Converter (TDC) output with a threshold limit. With 2.5 GHz at the LVDS output, the measured phase noise performance is -101 dBc/Hz at 10 kHz and -99 dBc/Hz at 100 kHz offset frequencies. An integrated phase jitter of 460 fs is measured using the on-chip oscillator. When using a 48 MHz reference crystal, the overall dynamic power consumption is 90 mW at 1.2 V core and 2.65 V IO supplies, respectively. The radiation tolerance is validated up to a total-ionizing-dose (TID) level of 1 kGy and a single-event latch-up (SEL) / single-event upset (SEU) level of 62.5 MeV·cm
²
/mg.