Processor SER Estimation with ACE Bit Analysis

Estimating the soft error rate (SER) for processors is imperative to adopt a proper hardening technique for increasing the system reliability. Aiming to estimate the functional error rates, we propose to scale the baseline SER estimated with physical memory sizes by the fraction of architecturally correct execution (ACE) bits of memory elements (SRAM, caches and registers). We compared the scaled SER with the measured SER under neutron irradiation for a multi-core processor and confirmed a good consistency.