Optimized Hazard Free Pipelined Architecture Block for RV32I RISC-V Processor

When analysing the two different types of processors available in market, RISC-based processors are more effective than CISC-based processors, for applications that demand higher speed and reduced power. RISC-based processors might be the ideal solution for pipelined instruction execution because of the reduced instruction complexity and reduced interdependence among the instructions. Pipelining improves any processor initial design by enhancing the processor’s speed, throughput, and thus performance. In any CPU, there are millions of instructions that must be implemented in a specific order, which takes a long time. Whenever an instruction is getting executed in a pipeline, it allows the following instruction to be executed without influencing the current instruction’s implementation, speeding up the process. The biggest downside of pipelining is the risk of data and control hazard, which can cause pipeline stalling. This paper presents a 32-bit RISC-V pipelined processor design that incorporates hazards elimination techniques such as data forwarding and branch prediction. To implement all of the instructions in the RISC-V processor’s basic integer instruction set, the processor is designed with five different stages of pipelining. In the proposed core the power consumption is reduced by 4% and speed is improved by 7.82% than the RISC-V processor developed for low power application reported in literature.