Maximizing performance and power density in PFC by using SMD packages with top-side cooling

This paper analyzes the efficiency of silicon MOSFETs in SMD packages with top-side cooling compared to bottom-side cooling packages in terms of thermal performance, lowering both thermal resistance and operating temperatures and improving switching performance due to the Kelvin pin. It will show how reducing the junction temperature helps to boost power efficiency due to a smoother variation of the main silicon MOSFET parameters due to temperature changes such as R
DS(on)
and V
GSth
level as well as reduces total conduction and switching losses.