Control and Data Hazard Resolving Schemes for Asynchronous RISC32 5-stage Pipeline Processor

Asynchronous micro-architectures are becoming an increasingly attractive design choice for building processors nowadays as they can exhibit very favorable power, speed, and electromagnetic interference (EMI) characteristics with respect to the synchronous micro-architectures. In most practical asynchronous processors, pipelining has been actively used as a strategy to boost the processor throughput. However, the control and data hazards caused by pipelining in an asynchronous processor may not be directly resolved using the traditional methods due to the lack of global synchronization. These hazards can wreak havoc on the processor performance if not being taken care of. In this paper, the asynchronous design solutions that have been devised to address the control and data hazards are briefly discussed. Besides, we present the viable schemes to resolve the corresponding control and data hazards, and implement the proposed schemes in the asynchronous version of the RISC32 5-stage pipeline processor. The introduced hazard resolving schemes do not require substantial changes in the regular processor pipeline structure, thus rendering them easy to adopt for use. In addition, this paper also reports a new data hazard detection scheme which can effectively identify the potential inter-instruction dependencies in an asynchronous pipeline without having any synchronization with other pipeline stages.