A novel integrated cooling packaging for high power density semiconductors

This work investigates a packaging solution for high power density semiconductors (> 200W /cm
²
), allowing for a dramatic reduction in size and complexity of power electronics modules. The multiple layers in standard packaging structures degrade the cooling efficiency due as they lengthen the path between dies and heatsinks. Here, we reduce the layer count by merging the ceramic substrate and the heat exchanger in a single part. CFD simulations and experimental validation are performed on a single-chip cooling packaging, and demonstrate a 10–20 % reduction in thermal resistance over more traditional cooling solutions.