A proposal for an FPGA-based graphical pipeline for virtual depth image generation

Currently, industrial robots can follow well-defined, repetitive tasks, which can substantially increase the productivity of the manufacturing processes. But the reaction to a dynamically changing environment is a frequently studied part of robotics. In our paper, we propose an FPGA-based virtual depth image generation process, which implements a modified graphical pipeline on the FPGA. Using the manipulator's current configuration and camera parameters, the robot's 3D model is transformed and projected into a 2D plane. During the rasterization stage, a virtual depth image is generated by determining the depth values for all the pixel coordinates. Although the FPGAs have limited capability for implementing a generic graphical pipeline, the described task-specific optimizations in the paper can provide a fast and energy-efficient implementation.