Transistor flaring in deep submicron-design considerations

The deep sub-micron regime has brought-up several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors, which causes the channel length to vary along the transistor width. This seriously impacts CMOS process self-alignment, causes transistor-matching issues, and makes accurate transistor modeling difficult. It can have significant adverse yield impact. In this paper, the effect, its consequences, and different solutions are examined. A methodology for modeling the effect of flaring on transistor performance is introduced. Different solutions for high density and high performance designs are proposed.