Design of CMOS Analog Front-End Electroencephalography (EEG) Amplifier with ±1-V Common-mode and ±10-mV Differential-mode Artifact Removal

This paper presents an analog front-end amplifier (AFEA), applied to Electroencephalography (EEG) recording, ready to directly drive the capacitor array of the following SAR ADC. In order to achieve lower noise, a capacitively-coupled chopper instrumentation amplifier (CCCIA) with chopper modulation is used in the AFEA to suppress flicker noise within the bandwidth. To avoid the stimulation artifact from saturating the amplifier, the artifact cancellation loop is employed. Additionally, the digital control for artifact cancellation loop enables the AFEA fast recover to normal operation after stimulation so that the AFEA can measure EEG signals right after stimulation. The EEG AFEA was fabricated in TSMC 0.18μm CMOS technology. From measurement results, the high-pass corner of the EEG AFEA is obtained at 0.341 Hz and the low-pass corner at 113 Hz. The EEG AFEA has the tunable gains of 60.4/69.6/79.2 dB. The input referred noise within the bandwidth is 0.839 μVrms. The measured THD is 0.155% under no artifact and 4.5% with 150-mV DC offset, ±1-V common-mode artifact (CMA), and ±10-mV differential-mode artifact (DMA) under 2-kHz and 2.01-kHz of temporally interfering stimulation (TIS). Additionally, the area and power consumption are 2.576 mm
²
and 83.2 μW, respectively.