Packaging of a 15-kV Silicon Carbide MOSFET With Insulation Enhanced by a Nonlinear Resistive Polymer-Nanoparticle Coating

Packaging of medium-voltage power semiconductor devices is challenging because the insulation materials are demanded to withstand extremely high electric-field stresses as well as to extract heat from the devices. One way to enhance the insulation of a device or module package without trading-off its thermal performance is by applying a thin layer of nonlinear resistive coating along the triple points on the package's insulated metal substrate. In this work, packaging of a 15-kV silicon carbide MOSFET was developed with the help of a nonlinear resistive polymer-nanoparticle coating applied along the copper edges of the package's direct-bond copper substrates. Without the coating, the substrate - a 1.0-mm alumina direct-bond copper substrate encapsulated in a silicone gel - had an average partial discharge inception voltage around 9.7 kV, 35% below the device's rated blocking voltage. With the coating, the partial discharge inception voltage was increased to 21.5 kV, a 120.5% improvement over that without the coating. Discrete 15-kV silicon carbide MOSFET packages were fabricated on the coated substrates, and their static electrical performance were characterized.