Analysis and Suppression of Voltage Oscillation of Solid-state Circuit Breaker Entering Active Region

To limit the fault current with power semiconductors based-DC solid-state circuit breaker (DC-SSCB), power semiconductors need to operate in the active region temporarily. During this interval, a severe voltage oscillation is observed, leading to the DC-SSCB overstress and eventually the failure. This paper aims to understand the mechanism causing the voltage oscillation and devise the solution to suppress it. First, a MATLAB/Simulink model is built with the comprehensive considerations of power semiconductors, parasitic, gate drive, and metal oxide varistor (MOV). Then a sensitivity study is performed to identify the critical impact factor(s) causing the voltage oscillation. Afterward, three suppression methods using enhanced gate drive circuitry are proposed and compared. Finally, test results based on a 2kV/1kA SSCB prototype demonstrate the effectiveness of the proposed oscillation mitigation method and the accuracy of the derived model.