Experimental fabrication of an ESF3 floating gate flash cell in an FD-SOI process

As minimum feature sizes in semiconductor processes are continuously decreasing, the parallel implementation of embedded non-volatile memory cells becomes increasingly complex for technology nodes below 28 nm. In this publication it is demonstrated the first ESF3 fabrication in an advanced SOI process using the buried oxide as a tunnel oxide. This enables a small cell area of
$0.086\ \mu\mathrm{m}^{2}$
with only few additional process steps and promising electrical data.