A Novel Differential Signal Routing Method for High-Speed and Large-Capacity DDR5 Dual-In-Line Memory Module

In DDR5 dual-in-line-memory-modules (DIMMs), a registering clock driver (RCD) receives control, address, clock signals from CPU and re-drives them to dynamic random access memories (DRAMs) through transmission lines on printed circuit board (PCB). Especially, clock signals operate at double data rate (DDR) which makes it substantially difficult to guarantee signal integrity (SI), whereas control, address signals operate at single data rate (SDR). As of now, JEDEC standards prescribes that the effective characteristic impedance of clock signals be as low as 22.5 Ohm for DDR5 DIMMs. With the strict restriction on the physical dimensions of PCB set forth by JEDEC, along with the fact high permittivity materials have already reached their limit, there is a limit to achieve low characteristic impedance with current PCB fabrication processes including increasing signal width, use of high permittivity materials and close reference plane. Therefore, we propose a novel differential signal routing method so as to achieve low characteristic impedance, and consequently wider bandwidth for high-speed and large-capacity DDR5 DIMMs. With the proposed structure on DIMM, the system bandwidth can be extended by 12%, allowing 7.2Gbps operation of DDR5 Mono DRAM.