Optimized FPGA-Based Datapath for the Iterative Design for the Factorial Function

The factorial function is used in computing approximate functions using for instance Taylor series. In this paper, we propose an optimized FPGA (Field Programmable Gate Arrays)-based datapath for the iterative realization of the factorial function. We compare the proposed design with the traditional one in terms of area and clock period and provide experimental results for Artix-7 Xilinx FPGAs using Xilinx Vivado 2020.2 as a synthesis tool. Our proposed approach excels on the traditional one.