Analysis and Design of Low Power Consumption 8T and 10T Full Adder CMOS Technology

All designers and engineers are familiar with the significance of adder subsystems. Therefore, engineers continue to perform research on them by integrating creative design ideas to boost the speed of the circuit and decrease its power consumption. In numerous digital data processing applications, such as microprocessors, and digital signal processors, adder logic cells are utilized. To implement Complementary Metal Oxide Semiconductor (CMOS) design techniques, many logic styles are employed. One example is the full adder, which is at the heart of every central processing unit and is essential to the way every type of computer processor works. In this paper, a design of 8 transistors and 10 transistors was developed using DSCH 3.5. Full adders are fundamental components of the ALU, which is the microprocessors' and Digital Signal Processing's logical and arithmetic unit. The Micro wind 3.5 tool is used to conduct simulation of the generated full adder design while operating at room temperature. The proposed 8T design shows $71.742\mu \mathrm{W}$ power consumption, the time delay is O.880ns and has 1.15 GHZ speed. The lOT design has less power consumption than 8T design. According to the findings of the investigation, the 8T design demonstrates superior speed efficiency and reduced power consumption when compared to the lOT design methodologies that were taken into consideration.