An Optimized MOS-Based High Frequency Charge-Controlled Memcapacitor Emulator

In this manuscript, an optimized MOS-based memcapacitor emulator is proposed using active elements and a resistor. The correctness of the proposed emulator is validated by performing pre and post layout analyses using
$Cadence~Virtuoso$
with
$TSMC~180~nm$
PDKs. Its area utilization and power consumption are
$2034.65~\mu m^{2}$
and
$1.86~mW$
, respectively. The maximum operating frequency of the proposed emulator is
$24~MHz$
. It is
$34\times $
,
$4\times $
, and
$8.189 \times $
better in terms of operating frequency, area, and power than its nearest contemporary memcapacitor emulator. A physical experiment is conducted to further verify the characteristics of the proposed emulator using
$CA3080$
analog ICs. An adaptive learning circuit using the proposed memcapacitor is designed to showcase its effectiveness for practical applications.