A Flux Controlled MOS-Based Optimized High Frequency Meminductor Emulator

In this paper, we propose an optimized meminductor emulator for high frequency operations. For the first time, the proposed meminductor emulator is designed using only MOS transistors making it realizable using monolithic IC fabrication. The numerical analysis of the proposed meminductor is performed employing Cadence Virtuoso with TSMC
$180~nm$
PDKs, and its behavior is verified with respect to different parameters, such as voltage, frequency, and process corner variations. Post layout analysis and physical experiments are also conducted to validate the proposed design. It is found that the area utilization and power consumption of the proposed meminductor are
$2350.67~\mu m^{2}$
and
$3.3~mW$
, respectively. Its maximum operating frequency is
$20~MHz$
, and it is
$3.42\times $
,
$2\times $
, and
$258\times $
more efficient in terms of area utilization, maximum operating frequency, and power consumption, respectively, compared to its nearest contemporary meminductors. Further, the applicability of the proposed meminductor is also verified by designing a chaotic oscillator to exhibit its utility in a wide range of applications.