A low-complexity DDS-based I/Q reference signal generation for capacitive sensing in 65nm CMOS

This work describes the results of the silicon evalu-ation of a direct digital synthesis (DDS) implementation, which was initially evaluated using virtual prototyping in SystemC AMS (IEEE 1666.1) and FPGA prototyping using VHDL (IEEE 1076). The block is part of a test chip produced in a 65nm CM OS technology. The result of the test chip is now available and allows the calibration of the model with measurement data. This model can then be re-used for future signal generation needs of capacitive sensor front-ends using carrier frequency based methods. Furthermore, the results of the design effort are presented and compared against another recently published design of a low complexity DDS in 65nm.