A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency

The maximum operating clock frequency of a digital system depends on static factors such as process variations and dynamic factors such as temperature and instantaneous supply voltage. The more accurately this maximum operating frequency can be known, the higher the clock frequency can be set thereby maximizing performance and minimizing the performance loss margin. We designed, fabricated, and measured circuits for the accurate estimation of the maximum operating frequency of a digital system. The circuits require: only 67.6 μm^2 die area in 32 nm CMOS, only a few clock cycles per measurement, minor modifications to the base system’s hardware, and small increases, if any, to the delays of the system’s critical paths. The technique also enables great potential flexibility in varying which circuits are tested. Measurements from fabricated silicon show an average 44%–54% reduction in frequency margin below the maximum operating clock frequency compared to the commonly-used critical path replica approach.