Speculative guardband: exploiting critical-delay variations across cached instructions

Several studies have been published to discuss methods of making components, such as CPUs, GPUs, and FPGAs, more energy efficient. Well-known techniques such as dynamic voltage and frequency scaling (DVFS) and power gating are alternatives since the supply voltage is directly related to power consumption. However, to guarantee correct operation without critical-path-timing violations, the systems must impose conservative static voltage guardbands. We propose to create a predictive guardband reduction technique for CPUs by analyzing the cached instructions. The contribution is expected to be the development of a machine learning solution capable of reducing average supply voltage levels by capturing the intrisic critical path variations according to which internal circuits are used by different sets of instructions.