High performance VLSI architecture for the modified SORT-N algorithm

Fast running sorting of streaming input data samples is very important in many applications such as order statistics, nonlinear filtering, MMax selective-tap adaptive filtering etc. This paper proposes a high performance VLSI architecture for the modified SORT-N algorithm for fast running sorting. Through analysis and also through synthesis results, we show that the critical path of the proposed architecture is almost independent of the sorting order N. ASIC synthesis results of the designed architecture shows that the proposed architecture has double the performance for N=1024 along with a reduction in area and power metrics compared to state-of-the-art architecture reported in literature and thus, it is potentially useful in real-time applications which have stringent throughput requirements.