A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme

This paper presents a 3bit/cycle 1GS/s8-bit SAR ADC with asynchronous ping-pong quantization scheme. With the proposed scheme, settling requirement of the reference voltages for multibit quantizer can be relaxed. In addition, loop-unrolled technique can be easily embedded in the SAR logic for higher speed without extra hardware consumption. Moreover, using the ping-pong scheme, the comparator offset can be corrected in background mode without extra calibration phase. The ADC is designed and simulated in 22nm CMOS process. Without calibration, the ADC achieves 33.4 dB SNDR. With offset calibration, the SNDR can be improved to 47.2 dB.