A Differential SPAD Array Architecture in 0.18 μm CMOS for HDR Imaging

We propose a scalable architecture for a differential single-photon avalanche diode (D-SPAD) array which generates measurements based on differential time-of-arrival in lieu of absolute time-of-arrival. This design addresses the throughput bottleneck in conventional sensors that record time-of-arrival statistics (such as histograms or raw arrival-time data) directly. In addition, this design also mitigates saturation at the pixel level and at the counter, making it an ideal candidate for use when the scene being imaged covers a high dynamic range (HDR). The differential nature of the data also obviates the need for large digital circuitry such as high bit depth counters or time to digital converters (TDCs). A prototype test structure of 16 pixels was fabricated in 0.18 $\mu$m CMOS, and we show images reconstructed from this chip that illustrate its capabilities.