Design of A 10-Bit, 2GS/s Current-Steering Digital-to-Analog Converter with OnLine Current Calibration

This paper presents a 2 GS/s digital-to-analog converter designed at 1 V in 28nm, targeting an ethernet PHY IP. The 10-bit current-steering digital-to-analog converter (DAC) is a segmented implementation, comprising 6+4 bits of binary-weighted and thermometer coded sections for the LSB and MSB codes respectively. The converter is based on a unit cell with cascoded current source and always-ON switches, to enhance static linearity performance and minimize dynamic errors. The calibration approach for amplitude correction partitions the DAC unit cells in larger blocks and compensate the tail current source variation with an internal current DAC (CALDAC). The design approach demonstrates good linearity with SFDR in the region of 70 dB in low-frequency input signals, which degrades to 49.4 dB at Nyquist frequency, and the DAC shows a maximum DNL of less than 0.5. The maximum differential output swing is 0.35 $\mathrm{V}_{\mathrm{pp}}$