Impact of Gate Dielectric Deposition Temperature on p-type Inversion Channel MOSFETs fabricated on GaN-on-Si

P-type inversion channel planar metal-oxide-semiconductor field-effect-transistors (MOSFETs) have been fab-ricated on 150 mm GaN-on-Si wafers. It is demonstrated that the deposition temperature during low pressure chemical vapor deposition of the gate dielectric has a strong impact on the tran-sistor behavior. By using metal-oxide-semiconductor capacitors on bare silicon, it is verified that the bulk oxide quality does not deteriorate when deposition temperature is reduced. On GaN, however, the variation of deposition temperature below and above the decomposition temperature of GaN results in fundamentally different transistor characteristics: field effect mobilities from 17 to 55 cm
²
/Vs have been obtained for threshold voltages decreasing from 8.0 to −3.2 V, respectively. Furthermore, the effect of the magnesium doping concentration in the p-GaN layer is evaluated.