Fully Integrated Multi-layer Stacked Structure of Integrated Inductor with Patterned Ground Shield

In this work, we propose fully integrated multi-layer stacked topology of asymmetrical inductor with patterned ground shield (PGS), which also serves as capacitor. The main aim of the study is efficient usage of limited chip area for integrated passive components by challenging layout properties of asymmetrical integrated inductor and integrated MOS capacitor and enhancing their main electrical properties. Several principles of geometry modifications(vertical and horizontal parallelization, slicing, tapering, equal path lengths) were applied to a four-turn octagonal asymmetrical integrated inductor with the series DC resistance
$R_{L}= 1.75\Omega$
and inductance
$L=11.66 nH$
on low frequencies. Remaining area under integrated inductor was used for a capacitor with capacitance
$C_{PGS}= 1.6 nF$
and the equivalent series resistance
$R_{C}= 7.25\Omega$
. The whole structure was designed in a standard 65nm CMOS technology for use in a switched DC-DC power converter working in MHz-range for a Photovoltaic (PV) Energy Harvester (EH).